Publish Date : 8th October, 2020
Post Name: Trainee Engineer, Layout Department
Number of Position: 10
- Use industry-grade IC Design and Verification software and flow.
- Layouts for different memory blocks using the latest technology nodes.
- Floorplanning, architecture definition, and physical layout implementation against the schematic design of standard cells.
- Work on layout verification parts like LVS, DRC, and others.
Employment Status: Full-Time
- B.Sc/ M.Sc in EEE from any reputed university
- Must have knowledge on Electronics, VLSI, Solid State Device physics, Finfet
- Knowledge on Cadence tool will be treated as an extra qualification
Additional Job Requirements
- Willing to stay at least 3 years
- Excellent teamwork capability
- Quick learner
- Good Communication Skill both oral and written
- Able to work under stress and multitasking capable
- Leadership capabilities
- Willing to build a career in VLSI industry
- Able to work with teams from different locations and time zones
- Good analytical and debugging capabilities is a must
How to Apply
Please submit your CV to email@example.com
Write the post name on the subject of the mail.
Application Deadline: October 23, 2020