Publish Date : 20th September, 2020
Post Name: Trainee Engineer, IC Physical Design
Required Number of Position: 05
Physical Design Engineer implements the entire SoC design flow from RTL to GDS to create a design database ready for manufacturing with special focus on power, performance & area optimization utilizing the next generation state of the art process technology.
- Perform physical design implementation which includes Floorplanning, Power Planning, Clock Tree Synthesis, Place and Route, ECO, Equivalency checks
- Timing, physical & electrical verification, driving the signoff closure meeting schedule and design goals
- Prepare deliverables & perform QA
- Communicate with the logic designers to develop timing, power and area design targets, and explore design tradeoffs for physical design closure.
- Develop flow and methodologies for physical design and automation scripts for various implementation steps.
Educational Qualification: B.Sc/ M.Sc in EEE from any reputed university
Additional Job Requirements:
- Willing to build career in VLSI industry
- Applicants are expected to complete courses which encompass the following topics–
○ Digital Devices and Electronics
○ VLSI Design with VHDL and/or Verilog
- Knowledge in IC Physical Design (PnR) will be treated as an extra qualification
- Familiarity with C/C++ or any programming language
- Knowledge of Linux environment and scripting languages like Perl, Python, TCL/Tk, shell scripting would be an advantage
- Able to handle multitasking and work under pressure
- Able to work with teams from different locations and time zones
- Good analytical and debugging capabilities is must
- Good communication skills, both oral and written
- Demonstrate good team player attitude
- High degree of initiative, enthusiasm and thinking out-of-the-box attitude
How to Apply
Please submit your CV to email@example.com. Write the post name in the subject of mail.
Application Deadline: October 5, 2020