Objective: The EEE Day VLSI Competition aims to spark interest and encourage student development in the field of Very-Large-Scale Integration (VLSI) circuit design. It provides a platform to showcase design skills, solve practical problems, and foster a competitive spirit for learning.
Eligibility:

• Members must be the current students of UIU.
• Students who have participated/completed the Junior Intra-University VLSI Design Competition or, VLSI Design course are highly encouraged to take participation.
Team Formation:

• Maximum 2 Members per team.
Date and Time:

Workshop
09/11/24 (Saturday)
11.00 am – 1.30 pm
Competition
09/11/24 (Saturday)
2.30 pm – 4.30 pm

Venue: VLSI LAB (Room No. #532), UIU.
Participation Fee: 300 Taka (Per team), [Per person- 150 Taka]
Registration deadline: Wednesday, 6th November 2024.
Rules:

1. Participants must bring their Student ID Card and confirmation of registration.
2. Participants can use resources such as books, articles, YouTube, online tools, etc., but AI cannot be used during the competition.
3. During the competition participants are not allowed to leave the room and communicate with anyone outside their own team.
4. Participants cannot use their personal devices (such as a mobile phone).

Topic:

CMOS Schematic and Layout Design.

Pre-Requisite:

1. Familiar with Cadence Virtuoso (Schematic XL, Layout XL, ADE L).
2. Familiar with basic Linux command.

Registration Link: https://forms.gle/37gqL54ev4FgQSdr8
Event Link:
https://facebook.com/events/s/eee-day-2024-department-of-eee/946141764003470/